TSC80251A1 Datasheet, PDF (30/166 Pages) TEMIC Semiconductors – Extended 8-bit Microcontroller with Analog Interfaces

TSC 80251A1
bits are provided externally (Port 0, Port 2). In this configuration, the program/code fits in one
read–only external memory segment and the data fits in another read–write external memory
segment. Each segment is replicated four times in one internal space.
Internal Spaces
Program/Code
Data
Read/Write Signals
PSEN#
RD#/WR#
Segments
FF:
FE:
01:
00:
FF:
FE:
01:
00:
Addresses
P2, P0
External Memory
2x64 Kbytes
00:, 01:, FE:, FF:
00:, 01:, FE:, FF:
Figure 1.8. Internal/external memory segments (RD1:0 = 11)
1.3. Memory Mapping
The specific internal memories of the TSC80251A1 derivatives fall into the following categories:
D 2 Configuration bytes,
D 24 Kbytes on–chip ROM or EPROM/OTP program/code memory,
D 1 Kbyte on–chip RAM data memory,
D Special Function Registers (SFRs).
1.3.1. Configuration Bytes
The Configuration bytes, CONFIG0 and CONFIG1, are detailed in Figure 1.11. and Figure 1.12.
During reset they are read from a specific ROM area. For the TSC87251A1 EPROM and OTPROM
versions, these bytes are programmable in an EPROM area (See “EPROM programming” chapter).
For the TSC83251A1 masked ROM versions, these bytes are additional information provided in a
masked ROM area. For the TSC80251A1 ROMless versions, these bytes are configured in factory
according to the part number (See “Ordering Information”). These bytes are not accessible by the
user during operation and they do not appear in the Memory Mapping of the TSC80251A1
derivatives.
II. 1.6
Rev. B (20/09/96)