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TSC80251G2D Datasheet, PDF (43/63 Pages) ATMEL Corporation – B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES
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TSC80251G2D
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
TLHAX(1)
TAVLL(1)
TLLAX
TQVWH
TWHQX
P0
A7:0
TAVWL1(1)
TAVWL2(1)
D7:0
Data Out
TWHAX
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 18. External Bus Cycle: Data Write (Non-Page Mode)
Waveforms in Page Mode
ALE
TLHLL(1)
TLLRL(1)
PSEN#(3)
TRLAZ
TLHAX(1)
TAVLL(1)
TLLAX
TRLDV(1)
TRHDZ1
TRHDX
P2
A15:8
D7:0
D7:0
TAVRL(1)
TAVDV1(1)
TAVDV2(1)
Instruction In
Instruction In
TAXDX
TAVDV3(1)
TRHAX
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
Page Miss(2)
Page Hit(2)
Notes:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2·TOSC);
a page miss requires two states (4·TOSC).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 19. External Bus Cycle: Code Fetch (Page Mode)
Rev. A - May 7, 1999
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