TSC80251G2D Datasheet, PDF (40/63 Pages) ATMEL Corporation – B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES

TSC80251G2D
Table 45. Bus Cycles AC Timings; V_DD= 4.5 to 5.5 V, T_A= -40 to 85°C
Symbol
Parameter
12 MHz
Min Max
16 MHz
Min Max
24 MHz
Min Max
T_OSC
1/F_OSC
83
62
41
T_LHLL ALE Pulse Width
78
58
38
T_AVLL Address Valid to ALE Low
78
58
37
T_LLAX
T_RLRH(1)
Address hold after ALE Low
RD#/PSEN# Pulse Width
19
11
3
162
121
78
T_WLWH WR# Pulse Width
165
124
81
T_LLRL(1) ALE Low to RD#/PSEN# Low
22
14
6
T_LHAX
T_RLDV(1)
T_RHDX(1)
T_RHAX(1)
T_RLAZ(1)
ALE High to Address Hold
RD#/PSEN# Low to Valid Data
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
99
70
40
146
104
61
0
0
0
0
0
0
0
0
0
T_RHDZ1 Instruction Float After RD#/PSEN# High
45
40
30
T_RHDZ2 Data Float After RD#/PSEN# High
215
165
115
T_RHLH1 RD#/PSEN# high to ALE High (Instruction)
49
43
31
T_RHLH2 RD#/PSEN# high to ALE High (Data)
215
169
115
T_WHLH WR# High to ALE High
215
169
115
T_AVDV1 Address (P0) Valid to Valid Data In
250
175
105
T_AVDV2 Address (P2) Valid to Valid Data In
306
223
140
T_AVDV3 Address (P0) Valid to Valid Instruction In
150
109
68
T_AXDX
T_AVRL(1)
Data Hold after Address Hold
Address Valid to RD# Low
0
0
0
100
70
40
T_AVWL1 Address (P0) Valid to WR# Low
100
70
40
T_AVWL2 Address (P2) Valid to WR# Low
158
115
74
T_WHQX Data Hold after WR# High
90
69
32
T_QVWH Data Valid to WR# High
133
102
72
T_WHAX WR# High to Address Hold
167
125
84
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T_OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T_OSC (N= 1..3).
Unit
ns
ns⁽²⁾
ns⁽²⁾
ns
ns⁽³⁾
ns⁽³⁾
ns
ns⁽²⁾
ns⁽³⁾
ns
ns
ns
ns
ns
ns
ns
ns
ns⁽²⁾⁽³⁾
ns⁽²⁾⁽³⁾
ns⁽³⁾
ns
ns⁽²⁾
ns⁽²⁾
ns⁽²⁾
ns
ns⁽³⁾
ns
40
Rev. A - May 7, 1999