TSC80251G2D Datasheet, PDF (30/63 Pages) ATMEL Corporation – B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES

TSC80251G2D
8.3 Signature Bytes
The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile
memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the
procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed
in Table 37.
Vendor
Architecture
Memory
Revision
Table 37. Signature Bytes (Electronic ID)
TEMIC
C251
32 Kbytes EPROM or OTPROM
32 Kbytes MaskROM or ROMless
TSC80251G2D derivative
Signature Address
30h
31h
60h
61h
Signature Data
58h
40h
F7h
77h
FDh
8.4 Programming Algorithm
Figure 9 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas:
q The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
q PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
q Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the programming sequence (see below).
q The voltage on the EA# pin must be set to V_DD.
q The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied
until the completion of this programming operation.
q The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB)
and the Least Significant Byte (LSB) of the address.
q The programming data are applied on Port 2.
q The EPROM Programming is done by raising the voltage on the EA# pin to V_PP, then by generating a low
level pulse on ALE/PROG# pin.
q The voltage on the EA# pin must be lowered to V_DD before completing the programming operation.
q It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the
voltage on the EA# pin has actually been lowered to V_DD before performing the verifying operation.
q PSEN# and the other control signals have to be released to complete a sequence of programming operations
or a sequence of programming and verifying operations.
Rev. A - May 7, 1999
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