TSC80251G2D Datasheet, PDF (26/63 Pages) ATMEL Corporation – B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES

TSC80251G2D
Table 32. Summary of Conditional Jump Instructions (2/2)
Jump if bit
Jump if not bit
Jump if bit and clear
JB <src>, rel
JNB <src>, rel
JBC <dest>, rel
Jump if accumulator is zero
Jump if accumulator is not zero
Compare and jump if not equal
JZ rel
JNZ rel
CJNE <src1>, <src2>, rel
Decrement and jump if not zero DJNZ <dest>, rel
(PC) ← (PC) + size (instr);
IF [src opnd= 1] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [dest opnd= 1] THEN
dest opnd ← 0
(PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A)= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A) ≠ 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd1 < src opnd2] THEN (CY) ← 1
IF [src opnd1 ≥ src opnd2] THEN (CY) ← 0
IF [src opnd1 ≠ src opnd2] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr); dest opnd ← dest opnd -1;
IF [ϕ (Z)] THEN (PC) ← (PC) + rel
Mnemonic <dest>, <src>⁽¹⁾
Comments
Binary Mode⁽²⁾ Source Mode⁽²⁾
Bytes States Bytes States
bit51, rel
JB
bit, rel
bit51, rel
JNB
bit, rel
Jump if direct bit is set
Jump if direct bit of 8-bit address location is set
Jump if direct bit is not set
Jump if direct bit of 8-bit address location is not set
3
2/5⁽³⁾⁽⁶⁾
3
2/5⁽³⁾⁽⁶⁾
5
4/7⁽³⁾⁽⁶⁾
4
3/6⁽³⁾⁽⁶⁾
3
2/5⁽³⁾⁽⁶⁾
3
2/5⁽³⁾⁽⁶⁾
5
4/7⁽³⁾⁽⁶⁾
4
3/6⁽³⁾
bit51, rel
Jump if direct bit is set & clear bit
3
4/7⁽⁵⁾⁽⁶⁾
3
4/7⁽⁵⁾⁽⁶⁾
JBC
bit, rel
Jump if direct bit of 8-bit address location is set and clear 5 7/10⁽⁵⁾⁽⁶⁾ 4
6/9⁽⁵⁾⁽⁶⁾
JZ
rel
Jump if ACC is zero
2
2/5⁽⁶⁾
2
2/5⁽⁶⁾
JNZ
rel
Jump if ACC is not zero
2
2/5⁽⁶⁾
2
2/5⁽⁶⁾
A, dir8, rel
Compare direct address to ACC and jump if not equal
3
2/5⁽³⁾⁽⁶⁾
3
2/5⁽³⁾⁽⁶⁾
CJNE
A, #data, rel
Rn, #data, rel
Compare immediate to ACC and jump if not equal
Compare immediate to register and jump if not equal
3
2/5⁽⁶⁾
3
2/5⁽⁶⁾
3
2/5⁽⁶⁾
4
3/6⁽⁶⁾
@Ri, #data, rel
Compare immediate to indirect and jump if not equal
3
3/6⁽⁶⁾
4
4/7⁽⁶⁾
DJNZ
Rn, rel
dir8, rel
Decrement register and jump if not zero
Decrement direct address and jump if not zero
2
2/5⁽⁶⁾
3
3/6⁽⁶⁾
3
3/6⁽⁴⁾⁽⁶⁾
3
3/6⁽⁴⁾⁽⁶⁾
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Rev. A - May 7, 1999
26