U6083B Datasheet, PDF (2/8 Pages) TEMIC Semiconductors – PWM Power Control with Interference Suppression

U6083B
Pin Description
V_{S 1}
GND ₂
V_{I 3}
Osc ₄
8 ^Output
7 ^{2 V}S
6 ^Sense
5 ^Delay
95 9944
Pin Symbol
Function
1
V_S Supply voltage V_S
2
GND IC ground
3
V_I Control input (duty cycle)
4
Osc Oscillator
5
Delay Short circuit protection delay
6
Sense Current sensing
7
2 V_S Voltage doubler
8
Output Output
Functional Description
Pin 1, Supply Voltage, V_s or V_Batt
Overvoltage Detection
Stage 1:
If overvoltages V_Batt > 20 V (typ.) occur, the external
transistor is switched off and switched on again at
V_Batt < 18.5 V (hysteresis).
Stage 2:
If V_Batt > 28.5 V (typ), the voltage limitation of the IC is
reduced from V_S = 26 V to 20 V. The gate of the external
transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the
event of overvoltage pulses occuring (e.g., load dump).
The short-circuit protection is not in operation. At V_Batt
approx. < 23 V, the overvoltage detection stage 2 is
switched off. Thus during overvoltage detection stage 2
the lamp voltage V_lamp is calculated to :
V_Lamp = V_Batt – V_S – V_GS
V_S = Supply voltage of the IC at overvoltage detection
stage 2
V_GS = Gate – source voltage of the FET
Undervoltage Detection
In the event of voltages of approximately V_Batt < 5.0 V,
the external FET is switched off and the latch for short-
circuit detection is reset.
 ^{A hysteresis ensures that the FET is switched on again at}
approximately V_Batt 5.4 V.
Pin 2, GND
Ground-Wire Breakage
W ^{To protect the FET in the case of ground-wire breakage,}
a 1 M resistor between gate and source it is recom-
mended to provide proper switch-off conditions.
Pin 3, Control Input
W ^{The pulse width is controlled by means of an external}
potentiometer (47 k ). The characteristic (angle of rota-
tion/duty cycle) is linear. The duty cycle can be varied
from 18 to 100%. It is possible to further restrict the duty
cycle with the resistors R₁ and R₂ (see figure 3).
In order to reduce the power dissipation of the FET and
to increase the lifetime of the lamps, the IC automatically
reduces the maximum duty cycle at Pin 8 if the supply
x ^{voltage exceeds V2 = 13 V. Pin 3 is protected against}
short-circuit to V_Batt and ground (V_Batt 16.5 V).
Pin 4, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C₂. It is
charged with a constant current, I, until the upper
switching threshold is reached. A second current source
is then activated which taps a double current, 2 I, from
the charging current. The capacitor, C₂, is thus discharged
at the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts once more.
Example for Oscillator Frequency Calculation:
Switching thresholds
a a ^{VT100 = High switching threshold (100% duty cycle)}
V_T100 = V_{S 1} = (V_Batt – I_S R₃)
1
a a ^{VT<100 = High switching threshold (< 100% duty cycle)}
V_T<100 = V_{S 2} = (V_Batt – I_S R₃)
2
a ^{VTL = Low switching threshold}
V_TL = V_{S 3} = (V_Batt – I_S R₃)
a₃
whereas
a a a ₁, ₂ and ₃ are fixed constant.
Calculation Example
The above mentioned threshold voltages are calculated
for the following values given in the data sheet.
W V_Batt = 12 V, I_S = 4 mA, R₃ = 150 ,
a a a ₁ = 0.7, ₂ = 0.67 and ₃ = 0.28.
2 (8)
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97