STLC5466 Datasheet, PDF (99/130 Pages) STMicroelectronics – 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED

1.2 Memory obtained with 1M x16 SDRAM circuit
STLC5466
Signals
A22
A21
NCE3
1
1
NCE2
1
0
NCE1
0
1
NCE0
0
0
Signals
A0
(or equivalent)
UDQM
1
LDQM
0
The Address bits delivered by the Multi-HDLC for 1M x n SDRAM circuits are:
ADM11 for Bank select corresponding with A20 delivered by the µP
ADM0/10 for Row address inputs corresponding with A9/19 delivered by the µP
ADM0/7 for Column address inputs corresponding with A1/8 delivered by the µP
Figure 1-22: 4Mx16 SDRAM memory organisation
UDQM
LDQM
NCE3
7
6
ADM0/11, NWE, NRAS, NCAS,
MCLK are connected to each circuit
NCE2
5
4
NCE1
NCE0
3
2
1M x 16 circuit
two banks
1
0
512 Kwords (16 bits) by bank
DM8/15 DM0/7
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