STLC5466 Datasheet, PDF (111/130 Pages) STMicroelectronics – 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED

4 MICROPROCESSOR TIMING
4.1 ST9 family; MOD0 = 1, MOD1 = 0, MOD2 = 0
Figure 4-1: ST9 read cycle
STLC5466
NCS0/1
NDSACK1 /
READY
NAS /
ALE
NDS /
NRD
AD0/7
R/W /
NWR
t1
t3
t4
t12
t5
t6
A0/7
t9
t11
t7
D0/7
t2
t8
t10
tx
Parameter
T min
T max
Unit
t1
Delay ready /Chip Select (if t3 >t1), (30 pF)
Delay when immediate access
0
ns
98
ns
t2
Hold time Chip Select /Data Strobe
14
ns
t3
Delay ready /NAS (if t1 >t3), (30 pF)
Delay when immediate access
0
ns
98
ns
t4
Width NAS
20
ns
t5
Set up time Address /NAS
9
ns
t6
Hold time Address /NAS
9
ns
t7
Data valid before ready
0
ns
t8
Data bus at high impedance after Data Strobe (30 pF)
0
15
ns
t9
Set up time R/W /NAS
15
ns
t10
Hold time R/W /Data Strobe
15
ns
t11
Width NDS when immediate access
50
ns
t12
Delay NDS / NCS
5
ns
111/130