STLC5466 Datasheet, PDF (81/130 Pages) STMicroelectronics – 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED

LIST OF FIGURES
STLC5466
1 FIGURES associated with text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 1-1:
MHDLC Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 1-2:
Variable delay through the matrix with ITDM=1 . . . . . . . . . . . . . . . . . . . . 84
Figure 1-3:
Variable delay through the matrix with ITDM=0 . . . . . . . . . . . . . . . . . . . . 85
Figure 1-4:
Constant delay through the matrix with SI=1. . . . . . . . . . . . . . . . . . . . . . . 86
Figure 1-5:
Downstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 1-6:
Upstream switching at 32 kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 1-7:
Upstream and downstream switching at 16 Kbit/s . . . . . . . . . . . . . . . . . . 89
Figure 1-8:
D, C/I and Monitor channel path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 1-9:
GCI channel to/from ISDN channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 1-10:
From GCI channels to ISDN channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 1-11:
From ISDN channels to GCI channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 1-12:
Multi-HDLC connected to mP with multiplexed buses. . . . . . . . . . . . . . . . 94
Figure 1-13:
Multi-HDLC connected to mP with non multiplexed buses . . . . . . . . . . . . 94
Figure 1-14:
Microprocessor interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 1-15:
Microprocessor interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 1-16:
Microprocessor interface for MOROLA 68000 . . . . . . . . . . . . . . . . . . . . . 96
Figure 1-17:
Microprocessor interface for MOROLA 68020 . . . . . . . . . . . . . . . . . . . . . 96
Figure 1-18:
Microprocessor interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 1-19:
Microprocessor interface for INTEL 386EX. . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 1-20:
Ex1; different clocks for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . . . . 98
Figure 1-21:
Ex2; synchronous clock for Multi-HDLC and mP . . . . . . . . . . . . . . . . . . . 98
Figure 1-22:
4Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 1-23:
First example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . . 100
Figure 1-24:
Second example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . 101
Figure 1-25:
Third example, 8Mx16 SDRAM memory organisation . . . . . . . . . . . . . . 102
Figure 1-26:
Chain of n Multi-HDLC components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 1-27:
MHDLC clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 1-28:
VCXO frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 1-29:
The three circular interrupt memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2 CLOCK and TDMs TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 2-1:
Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . 106
Figure 2-2:
Synchronization signals received by the Multi-HDLC . . . . . . . . . . . . . . . 107
Figure 2-3:
GCI Synchro signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . 108
Figure 2-4:
V* Synchronisation signal delivered by the Multi-HDLC . . . . . . . . . . . . . 109
3 SDRAM MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-1:
Signals exchanged between SDRAM controller and SDRAM. . . . . . . . . 110
4 MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 4-1:
ST 9 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 4-2:
ST 9 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 4-3:
ST10 (C16x) read cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 4-4:
ST10 (C16x) write cycle; multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . . 114
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