PM0056 Datasheet, PDF (99/156 Pages) STMicroelectronics – This programming manual provides information

PM0056
The Cortex-M3 instruction set
3.9.3
where:
• ‘effect’ is one of:
IE: Clears the special purpose register.
ID: Sets the special purpose register.
• ‘iflags’ is a sequence of one or more flags:
i: Set or clear PRIMASK.
f: Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See Exception mask
registers on page 19 for more information about these registers.
Restrictions
The restrictions are:
• Use CPS only from privileged software, it has no effect if used in unprivileged software
• CPS cannot be conditional and so must not be used inside an IT block.
Condition flags
This instruction does not change the condition flags.
Examples
CPSID i
CPSID f
CPSIE i
CPSIE f
; Disable interrupts and configurable fault handlers (set PRIMASK)
; Disable interrupts and all fault handlers (set FAULTMASK)
; Enable interrupts and configurable fault handlers (clear PRIMASK)
; Enable interrupts and fault handlers (clear FAULTMASK)
DMB
Data Memory Barrier.
Syntax
DMB{cond}
where:
• ‘cond’ is an optional condition code, see Conditional execution on page 57.
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear, in program order, before the DMB instruction are completed before any explicit
memory accesses that appear, in program order, after the DMB instruction. DMB does not
affect the ordering or execution of instructions that do not access memory.
Condition flags
This instruction does not change the flags.
Examples
DMB ; Data Memory Barrier
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