PM0056 Datasheet, PDF (35/156 Pages) STMicroelectronics – This programming manual provides information

PM0056
The Cortex-M3 processor
Table 16. Properties of the different exception types (continued)
Exception
IRQ
number⁽¹⁾ number⁽¹⁾
Exception
type
Priority
Vector address
or offset⁽²⁾
Activation
14
-2
PendSV
Configurable⁽³⁾ 0x00000038
Asynchronous
15
-1
SysTick
Configurable⁽³⁾ 0x0000003C
Asynchronous
16-83
0-67
Interrupt (IRQ)
Configurable ⁽⁴⁾
0x00000040 and
above ⁽⁵⁾
Asynchronous
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other
than interrupts. The IPSR returns the Exception number, see Interrupt program status register on page 18.
2. See Vector table on page 36 for more information.
3. See System handler priority registers (SHPRx) on page 138.
4. See Interrupt priority registers (NVIC_IPRx) on page 125.
5. Increasing in steps of 4.
2.3.3
For an asynchronous exception, other than reset, the processor can execute another
instruction between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that Table 16 on page 34 shows as having
configurable priority, see:
• System handler control and state register (SCB_SHCSR) on page 140
• Interrupt clear-enable registers (NVIC_ICERx) on page 121
For more information about hard faults, memory management faults, bus faults, and usage
faults, see Section 2.4: Fault handling on page 40.
Exception handlers
The processor handles exceptions using:
Interrupt Service
Routines (ISRs)
Fault handlers
System handlers
Interrupts IRQ0 to IRQ67 are the exceptions handled by ISRs.
Hard fault, memory management fault, usage fault, bus fault are fault
exceptions handled by the fault handlers.
NMI, PendSV, SVCall SysTick, and the fault exceptions are all
system exceptions that are handled by system handlers.
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