PM0056 Datasheet, PDF (123/156 Pages) STMicroelectronics – This programming manual provides information

PM0056
Core peripherals
4.3.5
Interrupt clear-pending registers (NVIC_ICPRx)
Address offset: 0x00 - 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
The ICPR0-ICPR2 registers remove the pending state from interrupts, and show which
interrupts are pending.
31
30
29
28
27
26
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15
14
13
12
11
10
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
25
rc_w1
9
rc_w1
24
23
22
CLRPEND[31:16]
rc_w1 rc_w1 rc_w1
8
7
6
CLRPEND[15:0]
rc_w1 rc_w1 rc_w1
21
rc_w1
5
rc_w1
20
rc_w1
4
rc_w1
19
rc_w1
3
rc_w1
18
rc_w1
2
rc_w1
17
rc_w1
1
rc_w1
16
rc_w1
0
rc_w1
Bits 31:0 CLRPEND[31:0]: Interrupt clear-pending bits
Write:
0: No effect
1: Removes the pending state of an interrupt
Read:
0: Interrupt is not pending
1: Interrupt is pending
See Table 41: Mapping of interrupts to the interrupt variables on page 119 for the
correspondence of interrupts to each register bit.
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
DocID15491 Rev 5
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