PM0056 Datasheet, PDF (130/156 Pages) STMicroelectronics – This programming manual provides information

Core peripherals
PM0056
Bits 31:3 Reserved, must be kept cleared
Bit 2 DISFOLD
Disables folding of IT instructions:
0: Enables IT instructions folding.
1: Disables IT instructions folding.
Bit 1 DISDEFWBUF
Disables write buffer use during default memory map accesses:
0: Enable write buffer use: stores to memory is competed before next instruction.
1: Disable write buffer use.
Bit 0 DISMCYCINT
Disables interrupt of multi-cycle instructions:
0: Enable interruption latency of the processor (load/store and multiply/divide operations).
1: Disable interruptions latency.
4.4.2
CPUID base register (SCB_CPUID)
Address offset: 0x00
Reset value: 0x411F C231 (STM32F1 series)
Reset value: 0x412F C230 (STM32F2 and STM32L series)
Required privilege: Privileged
The CPUID register contains the processor part number, version, and implementation
information.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Implementer
Variant
Constant
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PartNo
Revision
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:24 Implementer: Implementer code
0x41: ARM
Bits 23:20 Variant: Variant number
The r value in the rnpn product revision identifier
0x1: r1
0x2: r2
Bits 19:16 Constant: Reads as 0xF
Bits 15:4 PartNo: Part number of the processor
0xC23: = Cortex-M3
Bits 3:0 Revision: Revision number
The p value in the rnpn product revision identifier, indicates patch release.
0x0: = p0
0x1: = p1
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