STLC5465B Datasheet, PDF (97/101 Pages) STMicroelectronics – MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

STLC5465B
IX - EXTERNAL REGISTERS (continued)
Receiver
Tx : Tx = 0, Receiver
A4/0 : Rx HDLC Channel 0 to 31
ERF : Error detected on Received Frame
An error such as CRC not correct, Abort, Overflow has been detected.
EOQ : End of Queue
The receive DMA Controller has encountered the current receive Descriptor with EOQ at ”1”.
DMA Controller is waiting ”Continue” from microprocessor.
HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the
microprocessor; it is waiting ”Continue” from the microprocessor.
BE : Buffer Filled
If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has
filled the current buffer with data from the received frame.
CFR : Correctly Frame Received
A receive frame is ended with a correct CRC. The end ofthe frame islocated in the last descriptor
if several Descriptors.
IX.5 - Receive Command / Indicate Interrupt
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
bit15
bit8 bit7
NS Nu S1 S0 G0 A2 A1 A0 Nu Nu
bit 0
C6/A C5/E C4/S1 C3/S2 C2/S3 C1/S4
This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS : New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts INTFOV bit at ‘1’ to generate an interrupt (IR Interrupt
Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
S0/S1 Source of the event:
S1
S0
G0
Word stored in shared memory
0
0
0
Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4
0
0
1
Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5
0
1
0
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 0 without
outgoing to DOUT4
0
1
1
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without
outgoing to DOUT5
1
0
0
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
channels (16 bits) of the GCI 0 (DOUT4) in transparent mode or not
1
0
1
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not.
1
1
X
Reserved
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