STLC5465B Datasheet, PDF (89/101 Pages) STMicroelectronics – MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

STLC5465B
VIII - INTERNAL REGISTERS (continued)
U,V,W,Z : These four bits define the different signals delivered by the MHDLC.
First Case : the external RAM circuit is DRAM (T = 1 or S = 1)
- U defines the time Tu comprised between beginning of cycle and falling edge of NRAS :
U = 1, Tu = 60ns - U = 0, Tu = 30ns
- V defines the time Tv comprised between falling edge of NRAS and falling edge of NCAS :
V = 1, Tv = 60ns - V = 0, Tv = 30ns
- W defines the time Tw comprised between falling edge of NCAS and rising edge of NCAS :
W = 1, Tw = 60ns - W = 0, Tw = 30ns
- Z defines the time Tz comprised between rising edge of NCAS and end of cycle :
Z = 1, Tz = 60ns - Z = 0, Tz = 30ns
The total cycle is Tu + Tv + Tw + Tz.
The different output signals are high impedance during 15ns before the end of each cycle.
Second Case : the external RAM circuit is SRAM (T = 0 or S = 0)
- U and V define a part of write cycle for SRAM : the time Tuv comprised between falling edge
and rising edge of NCE. The total of write cycle is : 15ns+Tuv + 15ns.
V
U
Tuv
0
0
0
1
30ns
60ns
1
0
1
1
90ns
120ns
- W and Z define a part of read cycle for SRAM : the time Twz comprised between falling edge
of NOE and rising edge of NOE. The total of read cycle is : Twz +30ns
Z
W
0
0
Twz
30ns
0
1
1
0
60ns
90ns
1
1
120ns
N.B. The different output signals are high impedance during 15ns before the end of each cycle. On the outside of each (DRAM
or SRAM) cycle all the outputs are high impedance or not in accordance with MBL bit (see ”MBL : Memory Bus Low
impedance”).
Memory
bit15
bit8 bit7
bit 0
P4E1 P4E0 P3E1 P3E0 P2E1 P2E0 P1E1 P1E0 Z
WV
U
T
S
R REF
After reset (E4F0)_H
P1 E0/1 : PRIORITY 1 for entity defined by E0/1
P2 E0/1 : PRIORITY 2 for entity defined by E0/1
P3 E0/1 : PRIORITY 3 for entity defined by E0/1
P4 E0/1 : PRIORITY 4 for entity defined by E0/1
Entity definition :
E1
E0
0
0
Rx DMA Controller
0
1
Microprocessor
1
0
Tx DMA Controller
1
1
Interrupt Controller
Entity
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