STLC5465B Datasheet, PDF (43/101 Pages) STMicroelectronics – MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 33 : The Three Circular Interrupt Memories
IBA
INITIALIZATION
BLOC K
IBA + 256
HDLC (Tx a nd Rx)
INTER RUPT QUEUE
IBA + 256
+ HDLC
Que ue Size
MON (Rx)
INTER RUP TQUEUE
IBA + 256
+ HDLC
Que ue S ize
+ MON
Que ue S ize
C/I (Rx)
INTER RUP T QUEUE
IBA + 254
III.9 - Watchdog
This function is used to control the activity of the
application. It is composed of a counter which
counts down from an initial value loaded in the
Timer register by the microprocessor.
If the microprocessor doesn’t reset this counter
before it is totally decremented, the external Pin
WDO is activated ; this signal can be used to reset
the microprocessor and all the application.
The initial time value of the counter is programma-
ble from 0 to 15s in increments of 0.25ms.
At the reset of the component,the counter is auto-
matically initialized by the value corresponding to
512ms which are indicated in the Timer register.
The microprocessor must put WDR (IDCR Regis-
ter) to”1” to reset this counter and to confirm that
the application started correctly.
In the reverse case, the WDO signal could be used
to reset the board a second time.
The FS signal (8kHz) divided by two or the XTAL1
signal (typically 32768kHz) divided by 8192 can be
selected to increment the counter. At reset the
watchdog is incremented by the XTAL1 signal.
III.10 - Reset
There are two possibilities to reset the circuit :
- by software,
- by hardware.
Each programmable register receives its default
value. After that, the default value of each data
register is stored in the associatedmemory except
for Time slot Assigner memory.
III.11 - Boundary Scan
The Multi-HDLC is equipped with an IEEE Stand-
ard Test Access Port (IEEEStd1149.1).The bound-
ary scan technique involves the inclusion of a shift
register stage adjacent to each component pin so
that signals at component boundaries can be con-
trolled and observed using scan testing principle.
Its intention is to enable the test of on board inter-
connections and ASIC production tests.
The external interface of the Boundary Scan is
composed of the signals TDI, TDO, TCK, TMS and
TRST as defined in the IEEE Standard.
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