STLC5465B Datasheet, PDF (55/101 Pages) STMicroelectronics – MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1
Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D
NCS0/1
t2
NDSACK 0/
DTAC K _/
NREADY
t1
t3
t4
NA S_/
ALE
t12
ND S/
NRD
t7
t8
D0/15
R/W /
NWR _t9
A0/15 / AD0/15
A16/23 NBHE
Symbol
Parameter
t1
Delay Not Ready/NRD (if NCS0/1 = 0), (30pF)
Delay when immediate access
t2
Hold Time Chip Select / NRD
t3
Delay Not Ready / NRD rising edge
Delay when immediate access
t4
Width ALE
t5
Set-up Time Address / ALE
t6
Hold Time Address /ALE
t7
Data valid after ready
t8
Data bus at high impedance after NRD (30pF)
t9
Set-up Time NBHE, Address A 16/23/ALE
t10 Hold Time NBHE / NRD
t12 Delay NRD / NCS
t10
V_DD = 5V
V _DD = 3.3V
VDD = 5V
V DD = 3.3V
Min.
0
10
0
20
5
Typ.
Max.
98
108
98
108
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
V _DD = 5V
5
V _DD = 3.3V 10
0
ns
ns
15
ns
0
15
ns
5
ns
10
ns
0
ns
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