PSD835G2V_07 Datasheet, PDF (92/118 Pages) STMicroelectronics – Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

Programming in-circuit using the JTAG/ISP interface
PSD835G2V
20.2
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by an JTAG command received
over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD signals instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming a Byte in
Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low
until a special JTAG command is executed or a chip Reset (RESET) pulse is received after
an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in Ready/Busy (PE4) on page 31.
TSTAT is High when the PSD device is in Read mode (primary and secondary Flash
memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles
are in progress, and also when data is being written to the secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals during a JTAG command.
20.3
Security and Flash memory protection
When the security bit is set, the device cannot be read on a Device Programmer or through
the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part
to a non-secured blank state. The Security Bit can be set in PSDsoft.
All primary and secondary Flash memory sectors can individually be sector protected
against erasures. The sector protect bits can be set in PSDsoft.
Table 48. JTAG port signals
Port E Pin
JTAG Signals
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
Description
Mode Select
Clock
Serial Data In
Serial Data Out
Status
Error Flag
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