PSD835G2V_07 Datasheet, PDF (52/118 Pages) STMicroelectronics – Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

PLDs
PSD835G2V
15.2
Decode PLD (DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external
components. The DPLD can be used to generate the following decode signals:
● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
● 1 internal SRAM Select (RS0) signal (three product terms)
● 1 internal CSIOP Select (PSD Configuration Register) signal
● 1 JTAG Select signal (enables JTAG/ISP on Port E)
● 2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD logic array
I /O PORTS (PORT A,B,C,F)
(INPUTS)
(32)
MCELLA.FB7-FB0 (FEEDBACKS)
(8)
MCELLB.FB7-FB0 (FEEDBACKS)
(8)
PGR0 - PGR7
(8)
A15-A0^(1,2)
(16)
PD3-PD0 (ALE,CLKIN,CSI)
(4)
PDN (APD OUTPUT)
(1)
CNTRL2-CNTRL0 ^(READ/WRITE CONTROL SIGNALS) (3)
RESET
(1)
RD_BSY
(1)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
FS0
3
FS1
3
FS2
3
FS3 _{8 PRIMARY FLASH}
3
MEMORY SECTOR
FS4 SELECTS
3
FS5
3
FS6
3
FS7
3
RS0
SRAM SELECT
CSIOP
PSEL0
PSEL1
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
JTAGSEL
AI02873E
1. The address inputs are A19-A4 in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, D or F.
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