PSD835G2V_07 Datasheet, PDF (1/118 Pages) STMicroelectronics – Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

PSD835G2V
Flash PSD, 3 V supply, for 8-bit MCUs
4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM
Features
■ Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
■ Dual bank Flash memories
– 4 Mbits of Primary Flash memory (8
uniform sectors, 64 Kbyte)
– 256 Kbits of secondary Flash memory with
4 sectors
– Concurrent operation: READ from one
memory while erasing and writing the other
■ 64 Kbit of battery-backed SRAM
■ 52 reconfigurable I/O ports
■ Enhanced JTAG serial port
■ PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■ 52 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
■ In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
TQFP80 (U)
■ Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■ Programmable power management
■ High endurance:
– 100 000 Erase/WRITE cycles of Flash
memory
– 1,000 Erase/WRITE cycles of PLD
– 15 year data retention
■ 3 V to 3.6 V single supply voltage
■ Standby current as low as 25 µA
■ Memory speed
– 90 ns Flash memory and SRAM access
time for V_CC = 3.0 V to 3.6 V
– 120 ns Flash memory and SRAM access
time for V_CC = 3.0 V to 3.6 V
■ ECOPACK® packages
April 2007
Rev 2
1/118
www.st.com
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