PSD835G2V_07 Datasheet, PDF (101/118 Pages) STMicroelectronics – Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

PSD835G2V
Figure 37. Input to Output Disable / Enable
INPUT
tER
INPUT TO
OUTPUT
ENABLE/DISABLE
Figure 38. Combinatorial Timing – PLD
AC and DC parameters
tEA
AI02863
CPLD INPUT
tPD
CPLD OUTPUT
AI07655
Table 58. CPLD combinatorial timing
Symbol
Parameter
Conditions
-90
Min Max
-12
Min Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
CPLD Input
t_PD
Pin/Feedback to CPLD
Combinatorial Output
38
43 + 4 + 20 – 6 ns
t_EA
CPLD Input to CPLD
Output Enable
43
45
+ 20 – 6 ns
t_ER
CPLD Input to CPLD
Output Disable
43
45
+ 20 – 6 ns
t_ARP
CPLD Register Clear
or Preset Delay
38
43
+ 20 – 6 ns
t_ARPW
CPLD Register Clear
or Preset Pulse Width
28
30
+ 20
ns
t_ARD
CPLD Array Delay
Any
macrocell
23
27 + 4
ns
1. Fast Slew Rate output available on Ports C and F.
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