TDA7333 Datasheet, PDF (9/21 Pages) STMicroelectronics – RDS/RBDS PROCESSOR

TDA7333
The demodulator is fed by the 57 KHz bandpass filter and interpolated multiplex signal. The input signal
passes a digital filter extracting the sinus and cosinus components, to be used for further processing.
The sign of both channels are used as input for the ARI indicator and for the 57 KHz PLL.
A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present, the 57 KHz
PLL is operating as a normal PLL, else it is operating as a Costas loop.
One part of the PLL is compensating the integral offset (frequency deviation between oscillator and input
signal).
One channel of the filter is fed into the half wave integrator. Two half waves are created, with a phase
deviation of 90 degrees. One wave represents the RDS component, whereas the other wave represents
the ARI component. The sign of both waves are used as reference for the bit PLL (1187.5 Hz).
The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which after integra-
tion and differential decoding represents the RDS data.
In a similar way a quality bit can be calculated. This is useful to optimize error correction.
The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 Mhz clock may be used by setting the
corresponding bit in rds_bd_ctrl register (cf page 13).
In order to optimize the error correction in the group and block synchronization module, the sensitivity level
of the quality bit can be adjusted in three steps (cf page15). Only bits marked as bad by the quality bit are
allowed to be corrected in the group and block synchronization module. Thus the error correction is directly
influenced by this setup.
The time constant of the 57KHz PLL and the 1187.5Hz PLL may be influenced by software (cf page13).
This is useful in order to achieve a fast synchronization after a program resp. frequency change (fast time
constant) and to get a maximum of noise immunity after synchronization (slow time constant).
The user may choose between 2 possibilities via bit rds_bd_ctrl[1] (cf page13):
a: Hardware selected time constant - In this case both pll time constants are reset to the fastest one with
a reset from the group and block synchronization module. If the software decides to resynchronize, it
generates a reset . Both PLL are set to the fastest time constant, which is automatically increased to
the slowest one. This is done in four steps within a total time of 215.6ms (256 RDS clocks).
b: Software selected time constant - In this case the time constant of both PLL can be selected individually
by software.PLL time constants can be set independently.
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