STBC02 Datasheet, PDF (9/39 Pages) STMicroelectronics – Automatic power path management

STBC02
Bump
Bump
name
Digital I/Os
nRESET
C2
RST_PENDING B2
RESET_NOW A1
SW1_I
F3
SW1_OA
E4
SW1_OB
E3
Switch matrix
SW2_I
E2
SW2_OA
F2
SW2_OB
NC
F1
C3-D3
Pin configuration (top through view)
Description
Smart reset output signal (open drain output). A pull-up
resistor (10 – 100 kΩ) is connected to LDO pin or to a
higher voltage
Reset output signal (totem pole output)
Smart reset input signal (referred to LDO level);
RESET_CLEAR when watchdog is enabled
Load switch SPDT1
input (1.8 V to 5 V
range)
Load switch SPDT1
output A
(enabled/disabled by
SWIRE)
Load switch SPDT1
output B
(enabled/disabled by
SWIRE)
Load switch SPDT2
input (1.8 V to 5 V
range)
Load switch SPDT2
output A
(enabled/disabled by
SWIRE)
If SPDT switches are used,
decoupling capacitors are
recommended on input and
output. Capacitor values
depend on application
conditions and requirements.
If not used, connect inputs and
outputs to GND
Load switch SPDT2
output B
(enabled/disabled by
SWIRE)
Not connected
Leave floating
DocID029261 Rev 2
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