STBC02 Datasheet, PDF (8/39 Pages) STMicroelectronics – Automatic power path management

Pin configuration (top through view)
2
Pin configuration (top through view)
Figure 2: Pin configuration top through view
STBC02
8/39
Bump
IN
BAT
Power
SYS
LDO
NTC
AGND
GND
ISET
Programming
IPRE
BATMS
Sensing
BATSNS
BATSNSFV
Digital I/Os
CEN
CHG
WAKE-UP
SW_SEL
Table 2: Pin description
Bump
name
Description
E5-F5
Input supply voltage. Bypass this pin to ground with a 10
µF capacitor
A5-B5
Battery positive terminal. Bypass this pin to GND with a
4.7 µF ceramic capacitor
C5-D5
System output. Bypass this pin to ground with 1 µF
ceramic capacitor
F4
LDO output. Bypass this pin to ground with 1 µF
ceramic capacitor
D1
Battery temperature monitor pin
B4
Analog ground
A3
GROUND
Connect together with the
same ground layer
A4
Fast charge current programming resistor
D4
Pre-charge current programming resistor
C4
Battery voltage measurement pin
B3
Battery voltage sensing. Connect as close as possible to
the battery positive terminal
A2
Floating voltage sensing. Connect as close as possible
to the battery positive terminal
B1
Charger enable pin. Active high. 500 kΩ internal pull-up
(to LDO)
E1
Charging/fault flag. Active low (open drain output)
D2
Shipping mode exit input pin. Active high. 50 kΩ internal
pull-down
C1
Load switch selection input (refer to LDO level)
DocID029261 Rev 2