STBC02 Datasheet, PDF (23/39 Pages) STMicroelectronics – Automatic power path management

STBC02
6.13.2
Functional pin description
If not used, it is recommended both the nRESET and the RESET_NOW pins are pulled
down via a 100 kΩ resistor connected to GND.
Watchdog section control pins
The watchdog functionality can be enabled or disabled by using SWIRE commands (#27
enabled, #26 disabled).
If enabled by asserting the SWIRE command, the RESET_CLEAR function, implemented
using the RESET_NOW pin, allows the nRESET pulses to be skipped when in a high logic
level state.
It is recommended a proper RESET_CLEAR signal is applied at least 100 µs before the
next scheduled nReset transition to a low level (it occurs every 4000 ms).
Should the watchdog function be enabled at least after having detected a valid VIN plus a
delay of 150 ms, an nRESET signal transitioning to a low level occurs after 4000 ms
starting from the RST_PENDING transitioning to a high level. To skip this nRESET pulse, a
high level RESET_CLEAR signal must be generated prior to (at least 100 µs) the expiration
of the 4000 ms counter triggered by the RST_PENDING transitioning to a high level.
The watchdog function can be disabled anytime through an SWIRE command (#26) and if
so, the relevant circuit block goes back to the smart reset functionality default state. For
more details refer to the following timing diagram.
The watchdog function works when the STBC02 is in battery mode too.
Figure 20: Watchdog timing diagram
6.14
SW1_OA, SW1_OB, SW1_I, SW2_OA, SW2_OB, SW2_I
SPDT load switches pins. Both of SPDT load switches are controlled by an internal
register, using the SWIRE interface. Each SPDT features a typical RDS(on) of 3 Ω. SPDT
load switches can be paralleled to reduce the series resistor as well as to increase the
allowable flowing current.
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