ST7FOXA0 Datasheet, PDF (88/123 Pages) STMicroelectronics – 8-bit MCU with single voltage Flash memory

Interrupts
ST7FOXA0
Caution:
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
11.3 Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
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● The I bit of the CC register is cleared.
● The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
● Writing “0” to the corresponding bit in the status register or
● Access to the status register while the flag is set followed by a read or write of an
associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 35. Interrupt processing flowchart
FROM RESET
I BIT SET?
N
Y
FETCH NEXT INSTRUCTION
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
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