ST7FOXA0 Datasheet, PDF (68/123 Pages) STMicroelectronics – 8-bit MCU with single voltage Flash memory

On-chip peripherals
ST7FOXA0
9.2.4
Low power modes
Mode
Slow
Wait
Active-Halt
Halt
Description
The input frequency is divided by 32
No effect on AT timer
AT timer halted except if CK0=1, CK1=0 and OVFIE=1
AT timer halted
9.2.5 Interrupts
) ^{Interrupt Event 1)}
ct(s Overflow Event
du ^{CMP Event}
Event
Flag
OVF
CMPFx
Enable
Control
Bit
OVFIE
CMPIE
Exit
from
Wait
Yes
Yes
Exit
from
Halt
No
No
Exit
from
Active-Halt
Yes²⁾
No
ro _{Note: 1 The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).}
P _{They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt}
te _{mask in the CC register is reset (RIM instruction).}
le _{2 only if CK0=1 and CK1=0}
roduct(s) ^{- Obso 9.2.6}
Register description
TImer Control Status Register (ATCSR)
Reset Value: 0000 0000 (00h)
7
0
0
0
CK1
CK0
Read/Write
OVF
OVFIE
0
CMPIE
te ^P Bits 7:5 = Reserved, must be kept cleared.
le_{Bits 4:3 = CK[1:0] Counter Clock Selection.}
so _{These bits are set and cleared by software and cleared by hardware after a reset. They}
Ob ^{select the clock frequency of the counter.}
Table 23. Counter clock selection
Counter Clock Selection
CK1
CK0
OFF
f_LTIMER (1 ms timebase @ 8 MHz)
f_CPU
Reserved
0
0
0
1
1
0
1
1
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