ST7FOXA0 Datasheet, PDF (58/123 Pages) STMicroelectronics – 8-bit MCU with single voltage Flash memory

I/O ports
ST7FOXA0
8.6
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 17. Description of interrupt events
Interrupt Event
Event flag
Enable
Control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event
-
DDRx
ORx
Yes
Yes
Obsolete ^{Product(s) - Obsolete Product(s) 8.7}
See application notes AN1045 software implementation of I²C bus master, and AN1048 -
software LCD driver
Device-specific I/O port configuration
The I/O port register configurations are summarized in Table 18.
Table 18. Port configuration
Port
Pin name
Input (DDR=0)
OR = 0
OR = 1
Output (DDR=1)
OR = 0
OR = 1
Port A
PA0:2, PA4:5 ⁽¹⁾
PA3 ⁽²⁾
floating
-
pull-up interrupt ⁽¹⁾
-
open drain
open drain
push-pull
push-pull
1. IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH modes. Refer
to 11.3.2: External Interrupt Control Register 2 (EICR2) on page 91.
2. After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0
and MUXCR1 registers. See Section 6.3.6: Multiplexed IO reset control register 1 (MUXCR1) on page 34
and Section 6.3.7: Multiplexed IO reset control register 0 (MUXCR0) on page 34
Table 19. I/O port register map and reset values
Address _Register
(Hex.)
Label
7
6
5
4
3
2
1
0
0000h
PADR
Reset
Value
MSB
0
0
0
0
0
0
LSB
0
0
0001h
PADDR
Reset
Value
MSB
0
0
0
0
1
0
LSB
0
0
0002h
PAOR
Reset
Value
MSB
0
0
0
0
0
0
LSB
1
0
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