M58WR032FT Datasheet, PDF (81/86 Pages) STMicroelectronics – 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory

M58WR032FT, M58WR032FB
APPENDIX D. COMMAND INTERFACE STATE TABLES
Table 40. Command Interface States - Modify Table, Next State
Command Input
Current CI State
Read
Array⁽²⁾
(FFh)
WP
setup
(3,4)
(10/40h)
DWP,
QWP
Setup
(3,4)
(35h,
56h)
Block
Erase,
Bank
Erase
Setup
(3,4)
(20h,
80h)
EFP
Setup
(30h)
Quad-
EFP
Setup
(75h)
Erase
Confirm
P/E
Read
Resume, Program/ Read ^Clear Electronic
Block Erase Status ^status signature,
Unlock Suspend Register ^Register Read CFI
confirm, (B0h)
(70h)
(5)
(50h)
Query
EFP
(90h, 98h)
Confirm
(D0h)
Ready
Ready
Program
Setup
Program
Setup
Erase Setup EFP Setup
Quad-EFP
Setup
Ready
Lock/CR Setup
Ready (Lock Error)
Ready
Ready (Lock Error)
OTP
Setup
Busy
OTP Busy
Setup
Program Busy
Program ^Busy
Program Busy
Program
Suspended
Program Busy
Suspend
Program Suspended
Program
Busy
Program Suspended
Setup
Ready (error)
Erase Busy
Ready (error)
Erase
Busy
Suspend
Erase
Suspended
Program in
Erase
Suspend
Erase Busy
Erase Suspended
Erase
Suspended
Erase Busy
Erase Busy
Erase Suspended
Setup
Program Busy in Erase Suspend
Program
in Erase
Suspend
Busy
Suspend
Program Busy in Erase Suspend
Program Suspend in Erase Suspend
Program
Busy in
Erase
Suspend
Program
Suspend in
Erase
Suspend
Program Busy in Erase Suspend
Program Suspend in Erase Suspend
Lock/CR Setup
in Erase Suspend
Erase Suspend (Lock Error)
Erase
Suspend
Erase Suspend (Lock Error)
Setup
Ready (error)
EFP Busy
Ready (error)
EFP
Busy
EFP Busy ⁽⁶⁾
Verify
EFP Verify ⁽⁶⁾
Quad
EFP
Setup
Busy
Quad EFP Busy ⁽⁶⁾
Quad EFP Busy⁽⁶⁾
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-
tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.
2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-
put.
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is
first EFP Address. Any other commands are treated as data.
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