D950-CORE Datasheet, PDF (81/89 Pages) STMicroelectronics – 16-Bit Fixed Point Digital Signal Processor DSP Core

D950-Core
Control Registers
Three 16-bit control registers are dedicated to the DMA controller interface. These are the
general control register, the address interrupt control register and the Mask sensitivity control
register. They are detailed as follows:
DGC: General control register
Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel
1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3). After reset, DGC default value is 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
DRW3 DBC1 DBC0
-
DRW2 DBC1 DBC0
-
DRW1 DBC1 DBC0
-
DRW0 DBC1 DBC0
DBC1/DBC0: Bus choice for data transfer
0 : X-bus (def.)
01: Y-bus
10: I-bus
11: reserved
DRWi:
Data transfer direction
0: Write access (def.)
1: Read access
DAIC: Address/Interrupt control register
Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel
1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3). After reset, DAIC default value is 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAI3 DLA3 DIP3 DIE3 DAI2 DLA2 DIP2 DIE2 DAI1 DLA1 DIP1 DIE1 DAI0 DLA0 DIP0 DIE0
DAIi:
DLAi:
DIPi:
Address increment
0: DCAi content unchanged (def.)
1: DCAi content modified according to DLAi state
Load address
0: DCAi content incremented after each data transfer (def.)
1: DCAi content loaded with DIA content if DCCi value is 0 or DCAi content
incremented if DCCi value not equal to 0
Interrupt pending
0: No pending interrupt on channel i (def.)
1: Pending interrupt on channel i (enabled if DIP_ENA input is high)
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