D950-CORE Datasheet, PDF (1/89 Pages) STMicroelectronics – 16-Bit Fixed Point Digital Signal Processor DSP Core

D950-CORE
16-Bit Fixed Point Digital Signal Processor (DSP) Core
PRELIMINARY DATA
s Performance
s 66 Mips - 15ns instruction cycle time
s Memory Organization
s HARVARD architecture
s Two 64k x 16-bit data memory spaces
s One 64k x 16-bit program memory space
s 2 stacks in data memory spaces
s Fast and Flexible Buses
s Two 16-bit address 16-bit data non-
multiplexed data buses
s One 16-bit address 16-bit data non-
multiplexed instruction bus
s Data Calculation Unit
s 16 x 16-bit parallel multiplier
s 40-bit barrel shifter unit
s 40-bit ALU
s Two 40-bit extended precision accumulators
s Fractional and integer arithmetic with support
for floating point and multi-precision
s 16-bit bit manipulation unit (BMU)
s Address Calculation Unit
s Two address calculation units with modulo
and bit-reverse capability
s 2 x 16-bit address registers
s 4 x 16-bit index registers
s 2 x 16-bit base and maximum address
registers for modulo addressing
s Program Control Unit
s 16-bit program counter
s 3 Hardware Loop Capabilities
s Power Consumption
s Single 3.3V power supply
s Low-power standby mode
s Electrical Characteristics
s Operating frequency down to DC
s Channels
s General purpose 8-bit I/O port
s Dedicated hardware for Emulation and Test,
IEEE 1149.1 (JTAG) interface compatible
DATA
CALCULATION
UNIT
6
ADDRESS
16
CALCULATION
XA-bus
16
16
UNIT
YA-bus
16
PROGRAM
CONTROL
3
UNIT
ID-bus
16
IA-bus
16
11
8
14
CONTROL PO/P7
TEST & EMULATION
s Peripherals and Memory
s Macrocells for peripherals such as the bus
switch unit, interrupt controller and DMA
controller
s Standard cells library, I/O library
s Memory generators for RAM and ROM
s Development Tools
s JTAG PC board with graphic windowed high
level source debugger for AS-DSP emulation
s Complete crash-barrier chain (assembler /
simulator / linker) running on PC and SUN,
s Complete GNU chain (assembler / simulator /
linker / C compiler / C debugger) for SUN
s VHDL model (SYNOPSYS & MENTOR)
4 September 1997
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice
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