D950-CORE Datasheet, PDF (70/89 Pages) STMicroelectronics – 16-Bit Fixed Point Digital Signal Processor DSP Core

D950-Core
7.2.4 BSU control registers
The BSU is software controlled by six control registers mapped in the Y-memory space. These
define the type of memory used, internal to external boundary address crossing and software
wait-states count.
There are 2 registers per memory space, making it possible to define 2 sets of boundries and
wait state numbers.
Figure 7.2 Default and User Mapping Examples
64K
EXTERNAL
63K
INTERNAL1
62K
INTERNAL0
0
DEFAULT MAPPING (RESET)
64K
EXTERNAL
VALUE 1
INTERNAL1
VALUE 1
VALUE 0
INTERNAL0
VALUE 0
0
USER MAPPING
(CAN CHANGE BY 1K STEP)
The BSU control registers include a reference address on bits 4 to 9, where the internal/
external memory boundary value is stored (see Figure 7.2), and software wait-states count on
bits 0 to 3, allowing up to 16 wait-states.
External addressing is recognized by comparing these address bits for each valid address
from IA, XA and YA, to the reference address contained into the corresponding control
register.
If the address is greater or equal to the reference value, an external access proceeds.
For the following examples, ‘-’ means RESERVED (read: 0, write: don't care)
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