TDA7571 Datasheet, PDF (8/21 Pages) STMicroelectronics – STPDACsw - Fully digital high efficiency power audio amplifier

Electrical specifications
TDA7571
Table 5.
Electrical characteristics (continued)
(V_S = ±25V, R_L = 4Ω, f = 1kHz, T_j = 25°C, F_S = 44.1kHz, Single-Ended, application circuit shown
in Figure 3, 2 x 65W/1 x 130W system, unless otherwise specified.)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
P_dt
Power dissipation of the external @ P_out = 25W, bridge
power transistors
configuration, 1x250W system
10
W
THD Total harmonic distortion
V_ohs Half scale output voltage
@ P_out = 10 W, single ended
@ P_out = 40 W, bridge
single-ended, output voltage
@ IN = −6dBFS
0.1
%
0.05
%
10
Vrms
E_n
Output noise @ IN = -999dBFS
"A" weighted, single-ended
“A” weighted, bridge
180
100
µV
DR Dynamic range
“A” weighted, -60dBFS, Single-
ended PLL option circuit
85
dB
“A” weighted, -60dBFS, Bridge
free running oscillation option
96
dB
S/N
Signal-to-noise ratio (noise floor)
"A" weighted, single-ended
“A” weighted, bridge
100
110
dB
Ge Gain error
f = 1kHz
1.5
dB
ΔG_e
Delta gain error between
channels
f = 1kHz
0.2
dB
c_t
V_gspth
Crosstalk
Threshold voltage of the
Pchannel V_gs sensor
(VSpx1 - VGpxs)
f = 1kHz, V_o = 1Vrms
60
dB
2.5
3
3.5
V
V_gsnth
Threshold voltage of the
Pchannel V_gs sensor
(VSnxs - VSnx1)
2.5
3
3.5
V
A_m
SVR
F_SW
V_il
V_ih
Mute attenuation
Supply voltage rejection
Switching frequency
3.3V Logic inputs low level
voltage
3.3V Logic inputs high level
voltage
V_o = 1Vrms
f = 100Hz, V_r = 0.5V
pin: ST-BY, MUTE, SD, WS,
SCK, MCLK bridge
80
90
dB
50
60
dB
F_S x 8
KHz
1.5
V
2.3
V
V_il 5V Logic inputs low level voltage pin: L/R, CD SEL1, CD SEL2, P/O,
D1, D2. (these pins are typically
V_ih
5V Logic inputs high level voltage ^{connected to the DGND or 5V}
dig pins)
3.5
1.5
V
V
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