M14C64 Datasheet, PDF (8/14 Pages) STMicroelectronics – Memory Card IC 64/32 Kbit Serial I²C Bus EEPROM

M14C64, M14C32
Figure 9. Read Mode Sequences
CURRENT
ADDRESS
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
RANDOM
ADDRESS
READ
ACK
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT
R/W
R/W
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
Note: 1. The seven most significant bits of the Device Select bytes of a Random Read (in the 1^st and 4^th bytes) must be identical.
Current Address Read
The memory has an internal address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The master must not acknowl-
edge the byte output, and terminates the transfer
with a STOP condition, as shown in Figure 9.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 9.
This is followed by another START condition from
the master and the device select is repeated with
the RW bit set to ‘1’. The memory acknowledges
this, and outputs the byte addressed. The master
must not acknowledge the byte output, and termi-
nates the transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. How-
ever, in this case the master does acknowledge
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