M14C64 Datasheet, PDF (7/14 Pages) STMicroelectronics – Memory Card IC 64/32 Kbit Serial I²C Bus EEPROM

Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by M14xxx
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send
Byte Address
STOP
M14C64, M14C32
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02165
ed. The transfer is terminated by the master
generating a STOP condition. Care must be taken
to avoid address counter ’roll-over’ which could re-
sult in data being overwritten. Note that, for any
byte or page write mode, the generation by the
master of the STOP condition starts the internal
memory program cycle. This STOP condition trig-
gers an internal memory program cycle only if the
STOP condition is internally decoded immediately
after the ACK bit; any STOP condition decoded
out of this "10^th bit" time slot will not trigger the in-
ternal programming cycle. All inputs are disabled
until the completion of this cycle and the Memory
will not respond to any request.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t_w) is indicated in Table 7, but the
typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.
The sequence, as shown in Figure 8, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a device select byte (first byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next in-
struction (the first byte of this instruction having
been sent during Step 1).
Read Operations
Read operations are independent of the state of
the WC pin. On delivery, the memory content is set
at all “1’s” (FFh).
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