AN977 Datasheet, PDF (7/17 Pages) STMicroelectronics – GUIDELINES FOR UPGRADING FROM THE ST92F120

GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.6 INTERNAL VOLTAGE REGULATOR
In the ST92F124/F150/F250, the core operates at 3.3V, while the I/Os still operate at 5V. In
order to supply the 3.3V power to the core, an internal regulator has been added.
Actually, this voltage regulator consists of 2 regulators:
– a main voltage regulator (VR),
– a low power voltage regulator (LPVR).
The main voltage regulator (VR) supplies the current required by the device in all operating
modes. The voltage regulator (VR) is stabilized by adding an external capacitor (300 nF min-
imum) on one of the two Vreg pins. These Vreg pins are not able to drive other external de-
vices, and are only used for regulating the internal core power supply.
The low power voltage regulator (LPVR) generates a non-stabilized voltage of approximately
VDD/2, with minimum internal static dissipation. The output current is limited, so it is not suffi-
cient for full device operation mode. It provides reduced power consumption when the chip is
in Low Power mode (Wait For Interrupt, Low Power Wait For Interrupt, Stop or Halt modes).
When the VR is active, the LPVR is automatically deactivated.
1.7 EXTENDED FUNCTION TIMER
The hardware modifications in the Extended Function Timer of the ST92F124/F150/F250 as
compared to the ST92F120 only concern the interrupt generation functions. But some specific
information has been added to the documentation concerning Forced Compare mode and
One Pulse mode. This information may be found in the updated ST92F124/F150/F250 Da-
tasheet.
1.7.1 Input Capture/Output Compare
On the ST92F124/F150/F250, the IC1 and IC2 (OC1 and OC2) interrupts can be enabled sep-
arately. This is done using 4 new bits in the CR3 register:
– IC1IE=CR3[7]: Input Capture 1 Interrupt Enable. If reset, Input Capture 1 interrupt is inhibit-
ed. When set, an interrupt is generated if the ICF1 flag is set.
– OC1IE=CR3[6]: Output Compare 1 Interrupt Enable. When reset, Output Compare 1 inter-
rupt is inhibited. When set, an interrupt is generated if the OCF2 flag is set.
– IC2IE=CR3[5]: Input Capture 2 Interrupt Enable. When reset, Input Capture 2 interrupt is in-
hibited. When set, an interrupt is generated if the ICF2 flag is set.
– OC2IE=CR3[4]: Output Compare 2 Interrupt Enable. When reset, Output Compare 2 Inter-
rupt is inhibited. When set, an interrupt is generated if the OCF2 flag is set.
Note: The IC1IE and IC2IE (OC1IE and OC2IE) interrupts are not significant if the ICIE (OCIE)
is set. In order to be taken into account, the ICIE (OCIE) must be reset.
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