AN977 Datasheet, PDF (6/17 Pages) STMicroelectronics – GUIDELINES FOR UPGRADING FROM THE ST92F120

GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.5 RESET AND CLOCK CONTROL UNIT (RCCU)
1.5.1 Oscillator
A new low power oscillator is implemented with the following target specifications:
– Max. 200 µamp. consumption in Running mode,
– 0 amp. in Halt mode,
Figure 1. ST92F120 Internal Oscillator
Figure 2. ST92F124/F150/F250 Internal Oscillator
OSCOUT
OSCIN
HALT
REF
CLOCK
INPUT
BUFFER
I_LOAD
R_POL
OSCIN
V_DD
CLOCK1
VR02086A
OSCOUT
1.5.2 PLL
One bit (bit7 FREEN) has been added to the PLLCONF register (R246, page 55), this is to en-
able Free Running mode. The reset value for this register is 0x07. When the FREEN bit is
reset, it has the same behaviour as in the ST92F120, meaning that the PLL is turned off when:
– entering stop mode,
– DX(2:0) = 111 in the PLLCONF register,
– entering low power modes (Wait For Interrupt or Low Power Wait for Interrupt) following the
WFI instruction.
When the FREEN bit is set and any of the conditions listed above occur, the PLL enters Free
Running mode, and oscillates at a low frequency which is typically about 50 kHz.
In addition, when the PLL provides the internal clock, if the clock signal disappears (for in-
stance due to a broken or disconnected resonator...), a safety clock signal is automatically
provided, allowing the ST9 to perform some rescue operations.
The frequency of this clock signal depends on the DX[0..2] bits of the PLLCONF register
(R246, page55).
Refer to the ST92F124/F150/F250 datasheet for more details.
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