RM0017 Datasheet, PDF (692/904 Pages) STMicroelectronics – The SPC560Bx and SPC560Cx is a new family

RM0017
Flash Memory
Figure 382. DFlash User Multiple Input Signature Register 4 (DFLASH_UMISR4)
Address offset: 0x00058
Reset value: 0x0000_0000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MS[159:144]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MS[143:128]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
Table 368. DFLASH_UMISR4 field descriptions
Description
Multiple input Signature, bits 159-128
These bits represent the MISR value obtained accumulating:
the 8 ECC bits for the even Double Word (on MS[135:128]);
the single ECC error detection for even Double Word (on MS138);
MS[159:128] _{the double ECC error detection for even Double Word (on MS139);}
the 8 ECC bits for the odd Double Word (on MS[151:144]);
the single ECC error detection for odd Double Word (on MS154);
the double ECC error detection for odd Double Word (on MS155).
The MS can be seeded to any value by writing the DFLASH_UMISR4 register.
28.6
28.6.1
Programming considerations
In the following sections, register names can refer to the CFlash or DFlash versions of those
registers. Thus, for example, the term “MCR” can refer to the CFLASH_MCR or
DFLASH_MCR based on context.
Modify operation
All modify operations of the flash memory module are managed through the flash memory
User Registers Interface.
All the sectors of the flash memory module belong to the same partition (Bank), therefore
when a Modify operation is active on some sectors no read access is possible on any other
sector (Read-While-Write is not supported).
During a flash memory modify operation any attempt to read any flash memory location will
output invalid data and bit MCR[RWE] will be automatically set. This means that the flash
memory module is not fetchable when a modify operation is active and these commands
must be executed from another memory (internal SRAM or another flash memory module).
If during a Modify Operation a reset occurs, the operation is suddenly terminated and the
Macrocell is reset to Read Mode. The data integrity of the flash memory section where the
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