RM0017 Datasheet, PDF (385/904 Pages) STMicroelectronics – The SPC560Bx and SPC560Cx is a new family

LIN Controller (LINFlex)
RM0017
Field
RMB
RBSY
RPS
WUF
DBFF
DBEF
DRF
DTF
Table 176. LINSR field descriptions (continued)
Description
Release Message Buffer
0 Buffer is free.
1 Buffer ready to be read by software. This bit must be cleared by software after reading data
received in the buffer.
This bit is cleared by hardware in Initialization mode.
Receiver Busy Flag
0 Receiver is idle
1 Reception ongoing
Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit
is set. In this case, user cannot program LINCR2[DTRQ] = 1.
LIN receive pin state
This bit reflects the current status of LINRX pin for diagnostic purposes.
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge
on the LINRX pin when:
– Slave is in Sleep mode
– Master is in Sleep mode or idle state
This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is
generated if WUIE bit in LINIER is set.
Data Buffer Full Flag
This bit is set by hardware and indicates the buffer is full. It is set only when receiving extended
frames (DFL > 7).
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Data Buffer Empty Flag
This bit is set by hardware and indicates the buffer is empty. It is set only when transmitting
extended frames (DFL > 7).
This bit must be cleared by software, once buffer has been filled again, in order to start
transmission.
This bit is reset by hardware in Initialization mode.
Data Reception Completed Flag
This bit is set by hardware and indicates the data reception is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error or framing error.
Data Transmission Completed Flag
This bit is set by hardware and indicates the data transmission is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error if IOBE bit is reset.
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