RM0017 Datasheet, PDF (203/904 Pages) STMicroelectronics – The SPC560Bx and SPC560Cx is a new family

Reset Generation Module (MC_RGM)
RM0017
Table 81. Destructive Event Status Register (RGM_DES) Field Descriptions
Field
Description
F_POR
Flag for Power-On reset
0 No power-on event has occurred since the last clear (due to either a software clear or a low-
voltage detection)
1 A power-on event has occurred
F_LVD27
Flag for 2.7 V low-voltage detected
0 No 2.7 V low-voltage detected event has occurred since either the last clear or the last power-
on reset assertion
1 A 2.7 V low-voltage detected event has occurred
F_SWT
Flag for software watchdog timer
0 No software watchdog timer event has occurred since either the last clear or the last power-on
reset assertion
1 A software watchdog timer event has occurred
F_LVD12_PD1
Flag for 1.2 V low-voltage detected (power domain #1)
0 No 1.2 V low-voltage detected (power domain #1) event has occurred since either the last clear
or the last power-on reset assertion
1 A 1.2 V low-voltage detected (power domain #1) event has occurred
F_LVD12_PD0
Flag for 1.2 V low-voltage detected (power domain #0)
0 No 1.2 V low-voltage detected (power domain #0) event has occurred since either the last clear
or the last power-on reset assertion
1 A 1.2 V low-voltage detected (power domain #0) event has occurred
Note:
Note:
The F_POR flag is automatically cleared on a 1.2 V low-voltage detected (power domain #0
or #1) or a 2.7 V low-voltage detected. This means that if the power-up sequence is not
monotonic (i.e the voltage rises and then drops enough to trigger a low-voltage detection),
the F_POR flag may not be set but instead the <register>F_LVD12_PD0,
<register>F_LVD12_PD1, or <register>F_LVD27 flag is set on exiting the reset sequence.
Therefore, if the F_POR, <register>F_LVD12_PD0, <register>F_LVD12_PD1, or
<register>F_LVD27 flags are set on reset exit, software should interpret the reset cause as
power-on.
In contrast to all other reset sources, the 1.2 V low-voltage detected (power domain #0)
event is captured on its deassertion. Therefore, the status bit F_LVD12_PD0 is also
asserted on the reset’s deassertion. In case an alternate event is selected, the SAFE mode
or interrupt request are similarly asserted on the reset’s deassertion.
203/904
Doc ID 14629 Rev 8