PSD813F1A Datasheet, PDF (69/111 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

PSD813F1A
RESET TIMING AND DEVICE STATUS AT RESET
Power-On Reset
Warm Reset
Upon Power-up, the PSD requires a Reset (RE- Once the device is up and running, the device can
SET) pulse of duration t_NLNH-PO (See Tables 67 be reset with a much shorter pulse of t_NLNH (See
and 68 for values) after V_CC is steady. During this Tables 67 and 68 for values). The same t_OPR time
period, the device loads internal configurations, is needed before the device is operational after
clears some of the registers and sets the Flash warm reset. Figure 35 shows the timing of the
memory or EEPROM into Operating mode. After power on and warm reset.
the rising edge of Reset (RESET), the PSD re- _{I/O Pin, Register and PLD Status at Reset}
mains in the Reset mode for an additional period,
t_OPR (See Tables 67 and 68 for values), before the
first memory access is allowed.
Table 33., page 70 shows the I/O pin, register and
PLD status during Power On Reset, Warm reset
and Power-down mode. PLD outputs are always
The PSD Flash or EEPROM memory is reset to _{valid during warm reset, and they are valid in Pow-}
the READ mode upon power up. The FSi and _{er On Reset once the internal PSD Configuration}
EESi select signals along with the write strobe sig- _{bits are loaded. This loading of PSD is completed}
nal must be in the false state during power-up re-
set for maximum security of the data contents and
typically long before the V_CC ramps up to operat-
ing level. Once the PLD is active, the state of the
to remove the possibility of a byte being written on
the first edge of a write strobe signal. The PSD au-
) ^{tomatically prevents write strobes from reaching}
t(s ^{the EEPROM memory array for about 5ms (tEEH-}
WL^{). Any Flash memory WRITE cycle initiation is}
c _{prevented automatically when VCC is below VLKO.}
rodu ^{Figure 35. Reset (RESET) Timing}
outputs are determined by the PSDabel equa-
tions.
te ^P V_CC
Obsolete ^{Product(s) - Obsole RESET}
V_CC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
tOPR
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