PSD813F1A Datasheet, PDF (22/111 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

PSD813F1A
READ
Under typical conditions, the microcontroller may Reading the OTP Row. There are 64 bytes of
read the Flash or EEPROM memory using READ One-Time-Programmable (OTP) memory that re-
operations just as it would a ROM or RAM device. side in EEPROM. These 64 bytes are in addition
Alternately, the microcontroller may use READ op- to the 32 Kbytes of EEPROM memory. A READ of
erations to obtain status information about a Pro- the OTP row is done with an instruction composed
gram or Erase operation in progress. Lastly, the of at least 4 operations: 3 specific WRITE opera-
microcontroller may use instructions to read spe- tions and one to 64 READ operations (see Table
cial data from these memories. The following sec- 8., page 20). During the READ operation(s), ad-
tions describe these READ functions.
dress bit A6 must be zero, while address bits A5-
Read Memory Contents. Main Flash is placed in
the READ mode after power-up, chip reset, or a
Reset Flash instruction (see Table 8., page 20).
The microcontroller can read the memory contents
of main Flash or EEPROM by using READ opera-
A0 define the OTP Row byte to be read while any
EEPROM sector select signal (EESi) is active. Af-
ter reading the last byte, an EEPROM Return in-
struction must be executed (see Table
8., page 20).
tions any time the READ operation is not part of an Reading the Erase/Program Status Bits. The
instruction sequence.
PSD provides several status bits to be used by the
Read Main Flash Memory Identifier. The main ^{microcontroller to confirm the completion of an}
Flash memory identifier is read with an instruction
composed of 4 operations:
t(s) ^{3 specific write operations and a READ operation}
(see Table 8). During the READ operation, ad-
c _{dress bits A6, A1, and A0 must be 0,0,1, respec-}
u _{tively, and the appropriate sector select signal}
d _{(FSi) must be active. The Flash ID is E3h for the}
ro PSD. The MCU can read the ID only when it is ex-
P ecuting from the EEPROM.
te ^{Read Main Flash Memory Sector Protection}
Status. The main Flash memory sector protection
le _{status is read with an instruction composed of 4}
o _{operations: 3 specific WRITE operations and a}
s _{READ operation (see Table 8., page 20). During}
b _{the READ operation, address bits A6, A1, and A0}
O _{must be 0,1,0, respectively, while the chip select}
- _{FSi designates the Flash sector whose protection}
) _{has to be verified. The READ operation will pro-}
t(s ^{duce 01h if the Flash sector is protected, or 00h if}
the sector is not protected.
uc The sector protection status for all NVM blocks
d (main Flash or EEPROM) can be read by the mi-
ro ^{crocontroller accessing the Flash Protection and}
PSD/EE Protection registers in PSD I/O space.
P _{See Flash Memory and EEPROM Sector}
te ^{Protect, page 30 for register definitions.}
erase or programming instruction of Flash memo-
ry. Bits are also available to show the status of
WRITES to EEPROM. These status bits minimize
the time that the microcontroller spends perform-
ing these tasks and are defined in Table 9. The
status bits can be read as many times as needed.
For Flash memory, the microcontroller can per-
form a READ operation to obtain these status bits
while an Erase or Program instruction is being ex-
ecuted by the embedded algorithm. See the sec-
tion entitled PROGRAMMING FLASH
MEMORY, page 27 for details.
For EEPROM not in SDP mode, the microcon-
troller can perform a READ operation to obtain
these status bits just after a data WRITE opera-
tion. The microcontroller may write one to 64 bytes
before reading the status bits. See the section en-
titled Writing to the EEPROM, page 24 for details.
For EEPROM in SDP mode, the microcontroller
will perform a READ operation to obtain these sta-
tus bits while an SDP write instruction is being ex-
ecuted by the embedded algorithm. See section
entitled EEPROM Software Data Protect
(SDP), page 24 for details.
ole Table 9. Status Bit
Obs^Device
FSi/
CSBOOTi
EESi
DQ7
DQ6
DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Flash
V_IH
V_IL
Data Polling
Toggle
Flag
Error
Flag
X
Erase
Timeout
X
X
X
EEPROM
V_IL
V_IH
Data Polling
Toggle
Flag
X
X
X
X
X
X
Note: 1. X = not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
3. FSi and EESi are active High.
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