PSD813F1A Datasheet, PDF (24/111 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

PSD813F1A
Writing to the EEPROM
EEPROM Software Data Protect (SDP). The
Data may be written a byte at a time to the EE-
PROM using simple write operations, much like
writing to an SRAM. Unlike SRAM though, the
completion of each byte write must be checked be-
fore the next byte is written. To speed up this pro-
cess, the PSD offers a Page write feature to allow
SDP feature is useful for protecting the contents of
EEPROM from inadvertent write cycles that may
occur during uncontrolled MCU bus conditions.
These may happen if the application software gets
lost or when VCC is not within normal operating
range.
writing of several bytes before checking status.
Instructions from the MCU are used to enable and
To prevent inadvertent writes to EEPROM, the ^{disable SDP mode (see Table 8., page 20). Once}
PSD offers a Software Data Protect (SDP) mode. ^{enabled, the MCU must write an instruction se-}
Once enabled, SDP forces the MCU to “unlock” ^{quence to EEPROM before writing data (much like}
the EEPROM before altering its contents, much ^{writing to Flash memory). SDP mode can be used}
like Flash memory programming.
for both byte and page writes to EEPROM. The
Writing a Byte to EEPROM. A write operation is
initiated when an EEPROM select signal (EESi) is
device will remain in SDP mode until the MCU is-
sues a valid SDP disable instruction.
true and the write strobe signal (WR) into the PSD ^{PSD devices are shipped with SDP mode dis-}
is true. If the PSD detects no additional writes with- ^{abled. However, within PSDsoft Express, SDP}
in 120µsec, an internal storage operation is initiat- ^{mode may be enabled as part of programming the}
ed. Internal storage to EEPROM memory
technology typically takes a few milliseconds to
t(s) ^complete.
The status of the write operation is obtained by the
c _{MCU reading the Data Polling or Toggle bits (as}
u _{detailed in section entitled READ, page 22), or the}
d _{Ready/Busy output pin (section Ready/Busy Pin}
ro (PC3), page 18).
P _{Keep in mind that the MCU does not need to erase}
te ^{a location in EEPROM before writing it. Erasure is}
performed automatically as an internal process.
le _{Writing a Page to EEPROM. Writing data to EE-}
o _{PROM using page mode is more efficient than}
bs ^{writing one byte at a time. The PSD EEPROM has}
a 64 byte volatile buffer that the MCU may fill be-
O _{fore an internal EEPROM storage operation is ini-}
- _{tiated. Page mode timing approaches a 64:1}
) _{advantage over the time it takes to write individual}
t(s ^bytes.
c _{To invoke page mode, the MCU must write to EE-}
u _{PROM locations within a single page, with no}
d _{more than 120µs between individual byte writes. A}
ro single page means that address lines A14 to A6
P ^{must remain constant. The MCU may write to the}
64 locations on a page in any order, which is de-
te termined by address lines A5 to A0. As soon as
le ^{120µs have expired after the last page write, the}
o ^{internal EEPROM storage process begins and the}
s MCU checks programming status. Status is
b_{checked the same way it is for byte writes, de-}
O^{scribed above.}
device with a device programmer (PSDpro).
To enable SDP mode at run time, the MCU must
write three specific data bytes at three specific
memory locations, as shown in Figure 7., page 25.
Any further writes to EEPROM when SDP is set
will require this same sequence, followed by the
byte(s) to write. The first SDP enable sequence
can be followed directly by the byte(s) to be writ-
ten.
To disable SDP mode, the MCU must write specif-
ic bytes to six specific locations, as shown in Fig-
ure 8., page 26.
The MCU must not be executing code from EE-
PROM when these instructions are invoked. The
MCU must be operating from some other memory
when enabling or disabling SDP mode.
The state of SDP mode is not changed by power
on/off sequences (nonvolatile). When either the
SDP enable or SDP disable instructions are is-
sued from the MCU, the MCU must use the Toggle
bit (status bit DQ6) or the Ready/Busy output pin
to check programming status. The Ready/Busy
output is driven low from the first write of AAh @
555h until the completion of the internal storage
sequence. Data Polling (status bit DQ7) is not sup-
ported when issuing the SDP enable or SDP dis-
able commands.
Note: Using the SDP sequence (enabling, dis-
abling, or writing data) is initiated when specific
bytes are written to addresses on specific “pages”
of EEPROM memory, with no more than 120µs
Note: Be aware that if the upper address bits (A14
to A6) change during page write operations, loss
of data may occur. Ensure that all bytes for a given
page have been successfully stored in the EE-
PROM before proceeding to the next page. Cor-
rect management of MCU interrupts during
between WRITES. The addresses 555h and
AAAh are located on different pages of EEPROM.
This is how the PSD distinguishes these instruc-
tion sequences from ordinary writes to EEPROM,
which are expected to be within a single EEPROM
page.
EEPROM page write operations is essential.
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