PSD813F1A Datasheet, PDF (1/111 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

PSD813F1A
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 5 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
■ DUAL BANK FLASH MEMORIES
Figure 1. Packages
– 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
– 256 Kbit Secondary EEPROM (4 Uniform
Sectors)
– Concurrent operation: read from one
memory while erasing and writing the
PQFP52 (M)
other
) ■ 16 Kbit SRAM
t(s ^{■ PLD WITH MACROCELLS}
c – Over 3,000 Gates Of PLD: DPLD and
u CPLD
d _{– DPLD - User-defined Internal chip-select}
ro decoding
P _{– CPLD with 16 Output Macrocells (OMCs)}
te ^{and 24 Input Macrocells (IMCs)}
■ 27 RECONFIGURABLE I/Os
le _{– 27 individually configurable I/O port pins}
so ^{that can be used for the following}
b functions (16 I/O ports configurable as
open-drain outputs):
- ^O MCU I/Os
) _{PLD I/Os}
t(s ^{Latched MCU address output; and}
c _{Special function I/Os}
u _{■ ENHANCED JTAG SERIAL PORT}
rod ^{– Built-in JTAG-compliant serial port allows}
full-chip In-System Programmability (ISP)
P _{– Efficient manufacturing allows for easy}
te ^{product testing and programming}
le ^{■ PAGE REGISTER}
o_{– Internal page register that can be used to}
s _{expand the microcontroller address space}
b _{by a factor of 256.}
O_{■ PROGRAMMABLE POWER MANAGEMENT}
PLCC52 (J)
TQFQ64 (U)
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
■ SINGLE SUPPLY VOLTAGE:
– 5V±10% for 5V
■ STANDBY CURRENT AS LOW AS 50µA
■ Packages are ECOPACK^®
October 2008
Rev 5
This is information on a product still in production but not recommended for new designs.
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