M58LR128HT Datasheet, PDF (64/112 Pages) STMicroelectronics – 128 Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst) 1.8 V supply Flash memories

DC and AC parameters
M58LR128HT, M58LR128HB
Figure 12. Single Synchronous Read AC waveforms
A0-A22
VALID ADDRESS
tAVKH
L
tLLKH
K⁽²⁾
tELKH
tKHQV
tELQV
E
tGLQV
tGLQX
G
DQ0-DQ15 ^Hi-Z
tELQX
WAIT⁽¹⁾
Hi-Z
tGLTV
VALID
tKHTV
tGHTZ
Ai12360b
1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock
signal, K, can be configured as the active edge. Here, the active edge is the rising one.
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