STLC60135 Datasheet, PDF (6/25 Pages) STMicroelectronics – TOSCA ADSL DMT TRANSCEIVER

STLC60135
PIN FUNCTIONS (continued)
Pin
Name
Type Supply
139
AFTXD_0
O VDD
140
AFTXD_1
O VDD
141
VSS
142
AFTXD_2
O VDD
143
AFTXD_3
O VDD
144
VDD
Driver
BT4CR
BT4CR
BT4CR
BT4CR
BS
Function
O Transmit data nibble
O Transmit data nibble
0V Ground
O Transmit data nibble
O Transmit data nibble
(VSS + 3.3V) Power Supply
I/O DRIVER FUNCTION
Driver
BD4CR
BD8SCR
IBUF
IBUFDQ
IBUFUQ
Function
CMOS bidirectional, 4mA, slew rate control
CMOS bidirectional, 8mA, slew rate control, Schmitt trigger
CMOS input
CMOS input, pull down, IDDq control
CMOS input, pull up, IDDq control
PIN SUMMARY
Mnemonic
Type BS Type Signals
Function
Power Supply
VDD
VSS
(VSS + 3.3V) Power Supply
0V Ground
ATC Interface
ALE
I
C
PCLK
I
I
CSB
I
I
BE1
I
I
WR_RDB
I
I
RDYB
OZ
O
INTB
O
O
AD
IO
B
OBC_TYPE
I-PD
I
1
Used to latch the address of the internal register to be accessed
1
Processor clock
1
Chip selected to respond to bus cycle
1
Address 1 (not multiplexed)
1
Specifies the direction of the access cycle
1
Controls the ATC bus cycle termination
1
Requests ATC interrupt service
16 Multiplexed Address/Data bus
1
Select between i960 (0) or generic (1) controller interface
Test Access Part Interface
TDI
I-PU
TDO
OZ
TCK
I-PD
TMS
I-PU
TRSTB
I-PD
1
refer to section
1
1
1
1
Analog Front End Interface
AFRXD
I
I
AFTXD
O
O
AFTXED
O
O
CLWD
I
I
PDOW N
O
O
CTRLDATA
O
O
MCLK
I
C
4
Receive data nibble
4
Transmit data nibble
4
Transmit echo nibble
1
Start of word indication
1
Power down analog front end
1
Serial data transmit channel
1
Master clock
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