STLC60135 Datasheet, PDF (21/25 Pages) STMicroelectronics – TOSCA ADSL DMT TRANSCEIVER

STLC60135
Table 3: Master Clock (MCLK) AC Electrical Characteristics
Symbol
F
Tper
Th
Parameter
Clock Frequency
Clock Period
Clock Duty Cycle
Test Condition
Table 4: AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol
Tv
Tc
Parameter
Data Valid Time
Data Valid Time
Test Condition
Table 5: AFRXD AC Electrical Characteristics
Symbol
Ts
Th
Parameter
Data setup Time
Data hold Time
Test Condition
Tests, Clock, JTAG Interface
17
- Mclk: Master Clock (35.328MHz) generated by
19
VCXO
21
- ATM receive interface, asynchronous clock gen-
23
erated by Utopia Master
24
- ATM transmit interface, asynchronous clock
25
generated by Utopia Master
27
- ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific in-
28
terface)
30
JTAG TP interface: Standard Test Access Port,
31
Used with the boundary scan for chip and board
32
testing.
33
This JTAG TAP interface consists in 5 signals:
34
TDI, TDO, TCK & TMS.
35
TSRTB: Test Reset, reset the TAP controller.
38
TRSTB is an active low signal.
39
41
Table 6: Boundary Scan Chain Sequence
42
44
Sequence
Number
Mnemonic
Pin BS Type
45
46
2
AD_0
B
3
AD_1
B
47
4
AD_2
B
48
6
AD_3
B
50
7
AD_4
B
51
52
9
AD_5
B
53
10
AD_6
B
55
12
AD_7
B
56
13
AD_8
B
58
14
AD_9
B
60
16
AD_10
B
Min.
40
Typ.
35.328
28.3
Max.
60
Unit
MHz
ns
%
Min. Typ. Max. Unit
0
10
ns
0
10
ns
Min. Typ. Max. Unit
5
ns
5
ns
AD_11
B
AD_12
B
PCLK
I
AD_13
B
AD_14
B
AD_15
B
BE1
I
ALE
C
CSB
I
WR_RDB
I
RDYB
O
OBC_TYPE
I
INTB
O
RESETB
I
U_RxData_0
B
U_RxData_1
B
U_RxData_2
B
U_RxData_3
B
U_RxData_4
B
U_RxData_5
B
VSS
U_RxData_6
B
U_RxData_7
B
U_RxADDR_0
I
U_RxADDR_1
I
U_RxADDR_2
I
U_RxADDR_3
I
U_RxADDR_4
I
GP_IN_0
i
GP_IN_1
I
U_RxRefB
O
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