STLC60135 Datasheet, PDF (2/25 Pages) STMicroelectronics – TOSCA ADSL DMT TRANSCEIVER

STLC60135
The STLC60135 can be splitted up into two differ-
ent sections. The physical one performs the DMT
modulation, demodulation, Reed-Solomon encod-
ing, bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for
the generic and ATM Transmission Convergence
(TC) layers. The generic TC consists of data
scrambling and Reed Solomon error corrections,
with and without interleaving.
The STLC60135 is controlled and programmed
by an external controller (ADSL Transceiver Con-
troller, ATC) that sets the programmable coeffi-
cients.
The firmware controls the initialization phase and
carries out the consequent adaptationoperations.
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Ptot
T_amb
Parameter
Supply Voltage
Total Power Dissipation
Ambient Temperature 1m/s airflow
Figure 2. Pin Connection
Transient Energy Capabilities
ESD
ESD (Electronic Discharged) tests have been
performed for the Human Body Model (HBM) and
for the Charged Device Model (CDM).
The pins of the device are to be able to withstand
minimum 1500V for the HBM and minimum 250V
for CDM.
Latch-up
The maximum sink or source current from any pin
is limited to 100mA to prevent latch-up.
Min Typ Max Unit
3.0
3.3
3.6
V
900 1400 mW
-40
85
°C
2/25
VSS
AD_0
AD_1
AD_2
VDD
AD_3
AD_4
VSS
AD_5
AD_6
VDD
AD_7
AD_8
AD_9
VSS
AD_10
AD_11
VDD
AD_12
VSS
PCLK
VDD
AD_13
AD_14
AD_15
VSS
BE1
ALE
VDD
CSB
WR_RDB
RDYB
OBC_TYPE
INTB
RESETB
VSS
144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109
1
108
2
107
3
106
4
105
5
104
6
103
7
102
8
101
9
100
10
99
11
98
12
97
13
96
14
95
15
94
16
93
17
92
18
91
19
90
20
89
21
88
22
87
23
86
24
85
25
84
26
83
27
82
28
81
29
80
30
79
31
78
32
77
33
76
34
75
35
74
36
73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD
SLT_REQ_F
SLT_DAT_S0
SLT_DAT_S1
SLT_DAT_F0
SLT_DAT_F1
VSS
SLT_FRAME_F
SLAP_CLOCK
SLR_VAL_F
SLR_DAT_F0
SLR_DAT_F1
SLR_VAL_S
VDD
SLR_DAT_S0
SLR_DAT_S1
SLR_FRAME_S
VSS
SLR_FRAME_F
U_TX_ADDR_0
U_TX_ADDR_1
U_TX_ADDR_2
VDD
U_TX_ADDR_3
U_TX_ADDR_4
U_TX_DATA_0
U_TX_DATA_1
VDD
U_TX_DATA_2
U_TX_DATA_3
U_TX_DATA_4
U_TX_DATA_5
VDD
U_TX_DATA_6
U_TX_DATA_7
VSS
D98TL367B