TDA9110 Datasheet, PDF (5/29 Pages) STMicroelectronics – LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

TDA9110
ABSOLUTE MAXIMUM RATINGS
Symbol
V_CC
VDD
V_IN
VESD
HSize Cur
Tstg
T_j
Toper
Parameter
Supply Voltage (Pin 29)
Supply Voltage (Pin 32)
Max Voltage on
Pin 12
Pin 5
Pin 16
Pin 7
Pins 8, 9, 14, 20, 22
Pin 15, 18, 23, 24, 25, 26, 28
Pins 1, 2, 3, 4, 30, 31
ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Discharge through 0Ω
Max. Sourced Current (Pin 28)
Max. Sunk Current (Pin 28)
Storage Temperature
Junction Temperature
Operating Temperature
Value
13.5
5.7
1.8
4.0
5.5
6.4
8.0
V_CC
V_DD
2
300
2.5
100
-40, +150
+150
0, +70
Unit
V
V
V
V
V
V
V
V
V
kV
V
mA
µA
o_C
o_C
o_C
THERMAL DATA
Symbol
Parameter
Rth (j-a) Junction-ambient Thermal Resistance
Max.
Value
65
Unit
o_C/W
SYNCHRO PROCESSOR
Operating Conditions (V_DD = 5V, T_amb = 25^oC)
Symbol
HsVR
MinD
Mduty
VsVR
VSW
VSmD
VextM
Parameter
Horizontal Synchro Input Voltage
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty Cycle
Vertical Synchro Input Voltage
Minimum Vertical Synchro Pulse Width
Maximum Vertical Synchro Input Duty Cycle
Maximum Vertical Synchro Width on TTL H/Vcomposite
Test Conditions
Pin 1
Pin 1
Pin 1
Pin 2
Pin 2
Pin 2
Pin 1
Min.
0
0.7
0
5
Typ.
Max.
5
25
5
15
750
Unit
V
µs
%
V
µs
%
µs
Electrical Characteristics (V_DD = 5V, T_amb = 25^oC)
Symbol
Parameter
Test Conditions Min. Typ. Max. Unit
VINTH Horizontal and Vertical Input Threshold Voltage
Low Level
0.8 V
(Pins 1, 2)
High Level
2.2
V
RIN Horizontal and Vertical Pull-Up Resistor
Pins 1, 2
200
kΩ
VOut Output Voltage (Pin 4)
Low level
High Level
0
V
5
V
TfrOut Falling and Rising Output CMOS Buffer
Pin 4, Cout = 20pF
200 ns
VHlock Horizontal 1st PLL Lock Output Status (Pin 4)
Locked
Unlocked
0
V
5
V
VoutT Extracted Vsync Integration Time (% of T_H) on H/V C0 = 820pF
26 35
%
Composite
I²C READ/WRITE
Electrical Characteristics (V_DD = 5V,T_amb = 25^oC)
Symbol
Parameter
I²C PROCESSOR
Fscl Maximum Clock Frequency
Tlow
Thigh
Vinth
Low period of the SCL Clock
High period of the SCL Clock
SDA and SCL Input Threshold
VACK Acknowledge Output Voltage on SDA input with 3mA
See also I²C Table Control and I2C Sub Address Control
Test Conditions Min. Typ. Max. Unit
Pin 30
Pin 30
Pin 30
Pins 30,31
Pin 31
400 kHz
1.3
µs
0.6
µs
2.2
V
0.4 V
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