TDA9110 Datasheet, PDF (17/29 Pages) STMicroelectronics – LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

TDA9110
OPERATING DESCRIPTION (continued)
Figure 9 : Principle Diagram
H-LOCKCAP
8
LOCK/UNLOCK
STATUS
PLL1F R0 C0
7
65
HSYNC
INPUT
INTERFACE
TRAMEXT
LOCKDET
COMP1
E2
High
Low
TRAMEXT
CHARGE
PUMP
PLL
INHIBITION
PHASE
ADJUST
VCO
OSC
I²C
HPOS
Adj.
Figure 10 : Details of VCO
Loop
Filter
7
(1.3V < V₇ < 6V)
I₀
2
I₀
4 I₀
6
R0
The control voltage of the VCO is between 1.33V
and 6V (see Figure 10). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on filter lowest value.
In order to increase this effective frequency range,
to a possiblerange of 1 to6.0 one canadda resistor
from Pin 6 to Href leading.
The synchro frequency must always be higher than
the free running frequency. For example, when
using a synchro range between 31kHz and 96kHz,
the suggested free running frequency is 25kHz.
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
which is I²C adjustable between 2.65V and 3.75V
(corresponding to ± 10%) (see Figure 11).
6.4V
1.6V
RS
FLIP FLOP
10 6.4V
C0
1.6V
0 0.875T_H T
Figure 11 : PLL1 Timing Diagram
H Osc
Sawtooth _7/8TH
1/8T_H
Phase REF1
6.4V
2.60V<Vb<3.80V
Vb
1.6V
H Synchro
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.60V and 3.80V. The PLL1
ensures the exact coincidence between the signals phase REF
and HSYNS. A ± T/10 phase adjustment is possible.
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